1. Technical Field
Embodiments described herein generally relate to processors. In particular, embodiments described herein generally relate to processors to operate on packed data operands responsive to instructions.
2. Background Information
Many processors have Single Instruction, Multiple Data (SIMD) architectures. In SIMD architectures, a packed data instruction, vector instruction, or SIMD instruction may operate on multiple data elements simultaneously or in parallel. The processor may have parallel execution hardware responsive to the packed data instruction to perform the multiple operations simultaneously or in parallel.
Multiple data elements may be packed within a register or memory location as packed data or vector data. For example, the bits of a register may be logically divided into a sequence of data elements. Representatively, a 256-bit packed data register may have four 64-bit data elements, eight 32-bit data elements, or sixteen 16-bit data elements. Each data element may represent a separate individual piece of data (e.g., a pixel value), which may be operated upon separately and/or independently of the others.
One type of packed data instruction is a packed shift instruction, which may cause the bits of each data element of a single source packed data to be shifted separately and/or independently of the others. Packed shift left, packed shift right logical, and packed shift right arithmetic instructions are known in the arts. For each bit shifted out of one end, the packed shift left and packed shift right logical instructions may cause a corresponding zero to be inserted at the other end. The packed shift right arithmetic instruction may cause a sign bit to be inserted for each bit shifted out the other end.